Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

CORDIC algorithm and its applications

openThe CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation.The CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation

Frequency Stability Improvement in Direct Digital Frequency Synthesis

The paper describes a digital frequency synthesizer that incorporates a novel method of the clock signal frequency versus temperature dependency compensation. The clock signal is derived directly from a dual mode crystal oscillator (DMXO). With introducing the method, synthesized signal frequency versus temperature instability below a0.15ppm can be obtained over a wide temperature range (between 45°C and +85°C). Since a temperature information is obtained directly from a crystal itself rather than from an external sensor, temperature offset and lag effects are eliminated

Electronics and data acquisition demonstrator for a kinetic inductance camera

A prototype of digital frequency multiplexing electronics allowing the real time monitoring of kinetic inductance detector (KIDs) arrays for mm-wave astronomy has been developed. It requires only 2 coaxial cables for instrumenting a large array. For that, an excitation comb of frequencies is generated and fed through the detector. The direct frequency synthesis and the data acquisition relies heavily on a large FPGA using parallelized and pipelined processing. The prototype can instrument 128 resonators (pixels) over a bandwidth of 125 MHz. This paper describes the technical solution chosen, the algorithm used and the results obtained

Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study

This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.Ministerio de Educación y Ciencia TEC2004-01752/MI

Classical sampling theorems in the context of multirate and polyphase digital filter bank structures

The recovery of a signal from so-called generalized samples is a problem of designing appropriate linear filters called reconstruction (or synthesis) filters. This relationship is reviewed and explored. Novel theorems for the subsampling of sequences are derived by direct use of the digital-filter-bank framework. These results are related to the theory of perfect reconstruction in maximally decimated digital-filter-bank systems. One of the theorems pertains to the subsampling of a sequence and its first few differences and its subsequent stable reconstruction at finite cost with no error. The reconstruction filters turn out to be multiplierless and of the FIR (finite impulse response) type. These ideas are extended to the case of two-dimensional signals by use of a Kronecker formalism. The subsampling of bandlimited sequences is also considered. A sequence x(n ) with a Fourier transform vanishes for |ω|&ges;Lπ/M, where L and M are integers with L<M, can in principle be represented by reducing the data rate by the amount M/L. The digital polyphase framework is used as a convenient tool for the derivation as well as mechanization of the sampling theorem

DIRECT DIGITAL CONTROL IN A COMPLEX OF SOFTWARE DESIGN OF DIGITAL CONTROL SYSTEMS

This article provides the functionality of creating direct digital control devices in the computer-aided design of digital automatic control systems (CAD of digital ACS), in a complex of software design of digital control systems (SDSDC complex) for automated process control systems. Technical tools are defined by the international standard IEC 61131-1: 2003 (Part 1: General data). The possibility of implementing SDSDC complex in direct digital control, single-cycle and multi-cycle ladder diagrams, identification of objects of management and synthesis of digital controllers in comparison with the international standard IEC 61131-3: 2003 (Part 3: Programming Languages) are evaluated. Users’ productivity is estimated as well as the possibility of its separation between the users at different stages of the design of digital systems of automatic control is assessed